Control Core

The core is the central part of the function daughter-cards. The idea is to keep a consistent architecture of the most complex part of the different cards, to enable code reuse and minimise complexity where possible.

The choice of CPU and FPGA is not set in stone, other parts are being studied.

Control Core simplified architecture


The control core consists of a fast 32-bit micro-controller coupled tightly to an FPGA via the FSMC (memory mapped) interface. The FPGA hosts a large SDRAM and acts as the memory controller. The SDRAM can be accessed by the micro through the FSMC interface. Additional functionality in the FPGA can be accessed via memory mapped registers, additional internal memories and direct interfaces such as SPI.

Additionally, the Core contains an PLL device, allowing multiple local clocks to be generated to clock both the uC and FPGA, but also the application. The clocking architecture allows the PLL to take input clocks from the FPGA or microcontroller as well as the front end. Fast clocks can also be delivered into the front end to be presented directly to the user.


The back-plane provides all power, configuration and control. It provides the master reference clocks, time stamp data, networking via Ethernet and USB as well as a general purpose digital and analog connection scheme to allow the cards to send signals to each other.

There are no additional connections into the system. Each card consists of only back-end (back-plane connection) and front-end (user connections)


The application section hosts the parts of the function that are not user-facing directly. This will usually form the majority of the card circuit.

Front End

The front end section hosts the user interface. It handles signal conditioning, protection and formatting. The front end provides the physical connectors that interface the function card to the user application circuit.