Work in ProgressDetails here are subject to random and sudden changes!
The ICESTORM toolchain is limited to Verilog input source (as far as I know.) Whilst it is possible to write modular Verilog, it’s not easy, and it’s a lot of work.
A better fit may be to compile Verilog from a higher-level input source with MyHDL.
This project by Jan Decaluwe enables description of hardware using Python. It is modular, and automatic. MyHDL generates compilable Verilog source code. The ICESTORM tools then take this directly to an FPGA bitstream. With a wrapper around the whole thing, we could easily make changes to python hardware descriptions be automatically applied to the hardware as you code.
Almost in real time
Incremental compilation of Verilog, followed by background PnR activity, would drastically shorten implementation time. If PnR could also be made incremental (or at least hierarchical) then it could be even faster!